Chiplets, RISC-V, and Europe's AI Silicon Ambition
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Chiplets, RISC-V, and Europe's AI Silicon Ambition
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In this episode of Tech Threads, Baya’s CCO, Nandan Nayampally talks with Cesc Guim, CEO of Openchip, about building next-generation processors and computing platforms in Europe, why chiplet-based design is becoming central to scalable, specialized architectures, and how RISC-V opens up flexibility that fixed-ISA approaches can't match.
They also dig into the hardest problem in modern system design: moving data efficiently between processors, accelerators, memory, and chiplets. At scale, performance depends less on adding compute and more on getting the interconnect right: bandwidth, latency, and efficiency for demanding AI workloads.
Cesc also shares his take on the challenges and opportunities and the thrill of building a semiconductor company in Europe, forming the right technology partnerships, and turning regional ambition into products that compete globally.
In this episode:
• How Openchip is approaching AI and HPC system design
• Why chiplets are becoming central to scalable, specialized architectures
• Where RISC-V fits in enabling open, differentiated designs
• Why interconnect performance is the bottleneck for AI system efficiency
• How partnerships, especially with critical pieces like Baya’s IP, cut complexity, risk, and time-to-market
• What Europe needs to convert semiconductor investment into competitive products
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