The fundamental physics of data movement are forcing a shift to new memory architectures for AI inference. Sudeep Bhoja, co-founder and CTO of d-Matrix, joins Vik to detail the company's journey from a non-consensus bet on memory-bound inference to a full-rack 3D-stacked DRAM solution. Sudeep explains the pivot from analog to digital in-memory compute, the system-level disaggregation strategies for their Corsair card, and how the next-generation Raptor chip integrates with Nvidia's ecosystem.

"Essentially, we got 16 times the capacity of SRAM, while we retained SRAM bandwidth."
— Sudeep Bhoja, d-Matrix

Presented by Crusoe: Fine-tune and serve open models without managing a single GPU. When we sat down with Crusoe’s product team, Austin asked: what will you do with my data? Their answer: They don’t touch or see it. Your training data is encrypted so even Crusoe’s own admins can’t see it, and the fine-tuned model is yours. Deploy on Crusoe in one click, or download and run it anywhere. Upload a dataset, pick an open model, and pay per token rather than per GPU hour. Run a few versions, compare them, and download the one that works best. Accounts are free, and get $5 in credit when you sign up. Try Serverless Fine-Tuning: https://semidoped.com/crusoe

Key Takeaways:

- The core problem in AI inference is a 1000x energy gap. Compute costs femtojoules per operation, but moving data from memory costs picojoules per bit.

- d-Matrix's first analog in-memory compute chip failed because it couldn't maintain 32-bit accumulation precision, forcing a pivot to a digital architecture.

- The Corsair card's digital in-memory compute delivers 150 TB/s of on-chip SRAM bandwidth — over 8x more than an Nvidia Blackwell GPU's 18 TB/s HBM.

- The next-gen Raptor chip stacks a logic die on a DRAM die, delivering 16x the capacity (32 GB) of the prior SRAM design while retaining ~100 TB/s bandwidth.

- This 3D stacking is over 10x more energy-efficient than HBM4, consuming just 0.37 pJ/bit versus an estimated 5 pJ/bit for an HBM4-plus-GPU system.

- Choosing the stacking order is a 'pick your poison' trade-off. d-Matrix put logic-on-top for better thermals, accepting a harder power delivery challenge through the DRAM.

- The go-to-market product is a full rack with 144 Raptor packages, aggregating 2.3 TB of high-bandwidth memory designed to drop into Nvidia's VR rack infrastructure.

Chapters:
0:00 Intro: The Cost of a Token
3:28 The 2019 Bet on Inference
7:43 Nighthawk: Analog In-Memory Compute
12:08 Why Analog Failed
19:02 Corsair: Digital In-Memory Compute
26:04 System Strategy: Speculative Decoding
37:05 Raptor: 3D Stacked DRAM
39:40 The 'Free Lunch' of 3D Stacking
45:00 Trade-off: Logic-on-Top vs DRAM-on-Top
54:14 Go-to-Market: The Nvidia VR Rack
1:03:17 The Future: Lightning & 4-High Stacks
1:12:45 The End State of Inference

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Marvell's potential acquisition of Lumentum is a strategic vertical integration play to capture the massive value optical components now unlock in the AI era. Andrew Schmitt and Scott Wilkinson of market research firm Signal AI join Austin and Vik to break down the deal's core drivers. They explain how Marvell could run the 'Broadcom playbook' by bundling DSPs and optics, even at the cost of competing with its own customers, and why Lumentum's future-facing assets like Optical Circuit Switches (OCS) and high-power lasers are just as critical as its current-gen transceivers.

This episode is presented by Crusoe. Crusoe's Serverless Fine-Tuning trains an open model like Llama, DeepSeek, or GLM on your own data, and you pay per million tokens, not per GPU hour. About $2 buys roughly 5M training tokens on smaller models. Get $5 in credit to start: https://semidoped.com/crusoe

Key Takeaways:

- The deal's driver is vertical integration, not securing laser capacity. Marvell wants to control the supply chain from chips to optics to co-design superior products for the fast-moving AI market.

- The economics have flipped. Optics margins have doubled from ~25% to nearly 50%, making them attractive for chipmakers to acquire — even if it means Marvell pays 20-30x what it might have cost years ago.

- Lumentum's real moat is manufacturing scale. While others can build a hundred 'unicorn' devices like 200G EMLs, Lumentum's advantage is its ability to produce them reliably by the million.

- The acquisition creates channel conflict. Marvell's DSP customers will now have to compete with a vertically integrated Marvell-Lumentum, a dynamic that has already pushed some players out of the coherent market.

- This is also a bet on future architectures. The deal secures Lumentum's critical assets for next-gen data centers, including Optical Circuit Switches (OCS) and high-power lasers for CPO and NPO.

- Lumentum has the capacity to do both. After a 4x expansion of its Indium Phosphide fab, it can supply a vertically integrated Marvell and continue selling lasers to the open market.

- A bidding war is likely. The guests speculate the news leak was intentional to attract other suitors like Nvidia, who could run the same vertical integration playbook.

Chapters:
0:00 Intro: Marvell & Lumentum
7:38 The Vertical Integration Driver
9:17 The Channel Conflict Problem
14:58 Transceiver Value Chain
17:38 Why Would Lumentum Sell?
21:23 Lumentum's InP Capacity
24:52 The Cost of Waiting
27:00 Manufacturing Scale Is the Moat
31:30 How AI Changed Component Value
33:43 CPO: The Integration Endgame
36:50 The 'Broadcom Playbook'
38:58 Prediction: A Bidding War

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Chapters:
0:00 Intro: Marvell & Lumentum
7:38 The Vertical Integration Driver
9:17 The Channel Conflict Problem
14:58 Transceiver Value Chain
17:38 Why Would Lumentum Sell?
21:23 Lumentum's InP Capacity
24:52 The Cost of Waiting
27:00 Manufacturing Scale Is the Moat
31:30 How AI Changed Component Value
33:43 CPO: The Integration Endgame
36:50 The 'Broadcom Playbook'
38:58 Prediction: A Bidding War

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Intel's EMIB technology represents a scalable, cost-effective advanced packaging solution that now serves as a core strategic differentiator for its foundry services. Ravi Mahajan, a distinguished engineer at Intel Foundry, joins Austin to detail EMIB's 20-year journey from a "science fiction" concept to a high-volume manufacturing reality. They discuss the principle behind EMIB, interconnect where you need it and only where you need it: small silicon bridges carry the fine-pitch die-to-die signals, while the organic substrate's thick metal still delivers power and everything else. They also cover its manufacturing advantages over CoWoS and Intel's forward-looking roadmap for active bridges and top-side optics.

This episode is presented by Crusoe. Crusoe's Serverless Fine-Tuning trains an open model like Llama, DeepSeek, or GLM on your own data, and you pay per million tokens, not per GPU hour. About $2 buys roughly 5M training tokens on smaller models. Get $5 in credit to start: https://semidoped.com/crusoe

"When first envisioned, this was almost science fiction because the bridge I was talking about is roughly half the thickness of an A4 sheet of paper. So imagine being able to manipulate tiny strips of silicon like that."
— Ravi Mahajan, Intel Foundry

Key Takeaways:

- EMIB was invented to outpace organic packages, whose wire escape density at the die edge improved only about 10% per generation. The principle Ravi keeps returning to is interconnect where you need it and only where you need it: fine-pitch silicon in small local patches at the die edges, with the organic substrate's thick metal still carrying power and everything else. Fine wires are a poor way to deliver power anyway, and small bridges cut from a wafer keep the silicon cost down.

- Bringing EMIB from concept to production required the convergence of five distinct technologies, including a custom 4-layer silicon process and handling dies half the thickness of an A4 sheet of paper.

- Intel strategically chose HBM as EMIB's first driver, betting that if it could solve for the highest-performance memory interconnect, the technology could then "waterfall down" to all other less demanding applications.

- EMIB's advantage over CoWoS is manufacturing scale. Silicon only where you need it means small bridges instead of a full-sized silicon interposer, avoiding its high cost and poor wafer utilization, which is critical for large, multi-reticle AI packages.

- The EMIB portfolio was planned from the start. The original patent included EMIB-T, which uses TSVs to solve the "torturous" power delivery path of routing power around the bridge instead of through it.

- EMIB is an Intel Foundry exclusive. Packaging dies from other foundries is logistically straightforward, positioning advanced packaging as a key strategic differentiator for Intel's services.

- Intel's future roadmap includes top-side optics, using the top surface of the package for optical I/O to complement the electrical I/O on the bottom, dramatically increasing total package bandwidth.

Chapters:
0:00 Intro: Ravi Mahajan
1:44 Pathfinding & The HIR Roadmap
7:58 The Two Drivers of EMIB
15:15 Decoupling I/O and Power
16:27 The 'Science Fiction' of EMIB
20:36 HBM as the Killer App
25:06 EMIB vs. CoWoS
31:44 Chiplets, UCIe, and Packaging Tiers
34:08 The EMIB Portfolio: T, M, Active
37:01 An Intel Foundry Exclusive
41:21 AI's Role in Packaging
43:26 Future: Top-Side Optics

Mentioned in this episode:

- NEW EPISODE: Synopsys’s Amazon Deal and GPT-Synopsys: Ravi Subramanian (Semi Doped episode): https://daily.semidoped.com/p/new-episode-synopsys-will-take-a

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